1. Field of the Invention
The present invention is generally in the field of fabrication of semiconductor devices. More particularly, the present invention is in the field of fabrication of heterojunction bipolar transistors.
2. Related Art
In a silicon-germanium (xe2x80x9cSiGexe2x80x9d) heterojunction bipolar transistor (xe2x80x9cHBTxe2x80x9d), a thin silicon-germanium layer is grown as the base of a bipolar transistor on a silicon wafer. The silicon-germanium HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon bipolar transistor. Cutoff frequencies in excess of 100 GHz, which are comparable to the more expensive gallium-arsenide based devices, have been achieved for the silicon-germanium HBT.
The higher gain, speed and frequency response of the silicon-germanium HBT are possible due to certain advantages of silicon-germanium, such as a narrower band gap and reduced resistivity. These advantages make silicon-germanium devices more competitive than silicon-only devices in areas of technology where superior speed and frequency response are required.
But as with other transistors, excess capacitance can detrimentally impact performance of the silicon-germanium HBT transistor, primarily by reducing its speed. One form of excess capacitance associated with the silicon-germanium HBT is emitter to base capacitance. The practical effect of a capacitor is that it stores electrical charges that are later discharged, and the extra time required to charge and discharge the excess capacitance slows down the transistor. Because the benefits of high gain and high speed can be compromised by such excess capacitance, it is a goal of silicon-germanium HBT design to reduce such excess capacitance to a minimum. For instance, by keeping the emitter to base capacitance low, improved transistor performance is achieved.
Capacitance develops, for example, when two plates made of an electrically conducting material are separated by a dielectric such as silicon dioxide (xe2x80x9cSiO2xe2x80x9d). In general, capacitance is determined by the geometry of the device and is directly proportional to the area of overlap between the conductive plates and inversely proportional to the distance, or thickness, separating the two plates. Generally, capacitance is calculated using the equation:
Capacitance (C)=xcex50kA/txe2x80x83xe2x80x83(Equation 1)
where xcex50 is the permitivity of free space, k is the dielectric constant of the dielectric separating the two plates, A is the area of overlap between the plates, and t is the thickness or separation between the two plates. From the equation, it is seen that reducing the area of overlap between the two plates could lower the capacitance. Alternatively, separating the plates with a dielectric material having a relatively lower dielectric constant k, or increasing the thickness t, of the dielectric material could also lower the capacitance.
FIG. 1 shows an NPN silicon-germanium HBT structure 100, which is used to describe the emitter to base capacitance, or emitter-base capacitance, found in a silicon-germanium HBT fabricated using conventional fabrication processes. Certain details and features have been left out of FIG. 1 which are apparent to a person of ordinary skill in the art. Structure 100 includes, among other components, collector 130, base region 120, and emitter 140. In exemplary structure 100, collector 130 is N type single-crystal silicon which can be deposited epitaxially using a reduced pressure chemical vapor deposition (xe2x80x9cRPCVDxe2x80x9d) process, and base region 120 is P type single-crystal silicon-germanium deposited epitaxially in a nonselective RPCVD process. As seen in FIG. 1, base region 120 is situated on top of, and forms a junction with, collector 130. Extending out from either side of base region 120 are extrinsic base region 122 and extrinsic base region 124. In exemplary structure 100, emitter 140, which is situated above and forms a junction with base region 120, is comprised of N type polycrystalline silicon. The interface between emitter 140, base region 120, and collector 130 is the active region of the silicon-germanium HBT. Active region width 145 is substantially the same as the distance between dielectric segment 172 and dielectric segment 174. As is known in the art, proper control of the dimension of active region width 145 is critical for optimal performance of the silicon-germanium HBT.
The portions of emitter 140 extending beyond active region width 145 overlap polycrystalline silicon segment 162 and polycrystalline silicon segment 164. The portions of emitter 140 extending beyond active region width 145 are referred to as extrinsic emitter region 142 and extrinsic emitter region 144. Thus, extrinsic emitter region 142 is the region of emitter 140 which is between dashed line 192 and the edge of emitter 140. Similarly, extrinsic emitter region 144 is the region of emitter 140 which is between dashed line 194 and the edge of emitter 140. As seen in FIG. 1, sandwiched between polycrystalline silicon segment 162 and extrinsic base region 122, and between polycrystalline silicon segment 164 and extrinsic base region 124 are dielectric segment 172 and dielectric segment 174. Besides defining active region width 145, dielectric segments 172 and 174 provide electrical isolation to emitter 140 from base region 120.
As further seen in FIG. 1, buried layer 114, which is composed of N+ type material, is formed in semiconductor substrate 110. Collector sinker 112, also composed of N+ type material, is formed by diffusion of heavily concentrated dopants from the surface of collector sinker 112 down to buried layer 114. Buried layer 114 and collector sinker 112 provide a low resistance electrical pathway from collector 130 through buried layer 114 and collector sinker 112 to a collector contact (not shown). Deep trench structures 116 and field oxide region 180, field oxide region 182, and field oxide region 184 provide electrical isolation from other devices on semiconductor substrate 110. Although field oxide regions 180, 182, and 184 comprise silicon dioxide in the present example, it is known in the art that field oxide regions 180, 182, and 184 could be other types of isolation, for example shallow trench isolation regions, deep trench isolation, or local oxidation of silicon, generally referred to as xe2x80x9cLOCOSxe2x80x9d.
Emitter to base capacitance (xe2x80x9cCebxe2x80x9d) in a silicon-germanium HBT is composed of intrinsic and extrinsic components. These intrinsic and extrinsic components of the emitter to base capacitance are shown in FIG. 1. Intrinsic Ceb 150 is between emitter 140 and single-crystal silicon-germanium base region 120 of the silicon-germanium HBT. Intrinsic Ceb 150 is the emitter-base junction capacitance inherent in the silicon-germanium HBT device and is determined by various fabrication parameters in the silicon-germanium HBT device. Therefore, intrinsic Ceb 150 can only be reduced by altering the fabrication parameters and the performance of the device itself. For example, reduction in intrinsic Ceb 150 could be achieved by making active region width 145 narrower, but such a modification to the device architecture would alter the performance properties of the device.
Continuing with FIG. 1, extrinsic components of emitter to base capacitance in a silicon-germanium HBT develop where extrinsic emitter region 142 and extrinsic emitter region 144 overlap, respectively, extrinsic base region 122 and extrinsic base region 124 directly through dielectric segment 172 and dielectric segment 174. More specifically, extrinsic Ceb 152 is between extrinsic emitter region 142 and extrinsic base region 122 through dielectric segment 172, while extrinsic Ceb 154 is between extrinsic emitter region 144 and extrinsic base region 124 through dielectric segment 174. The total value of emitter to base capacitance (xe2x80x9ctotal Cebxe2x80x9d) in a silicon-germanium HBT is thus the sum of intrinsic Ceb 150, extrinsic Ceb 152, and extrinsic Ceb 154.
Various methods aimed at reducing the total Ceb have been introduced, as known in the art, but these methods have not produced the level of reduction desired or, in other instances, are impractical to implement. For example, one method proposed involves reducing the geometries of the silicon-germanium HBT, particularly reducing the portions of the emitter that extend beyond the width of the active region and overlap extrinsic base regions. Unfortunately, such undesired overlapping can only be reduced to the extent permitted by current photolithography processes utilized to fabricate the emitter. Thus a certain amount of overlapping is unavoidable because of the limitation in resolution with current photolithography technology. Another proposed method is directed to reducing the area of the active region of the silicon-germanium HBT. Utilizing such a method would reduce intrinsic Ceb, but as discussed briefly above, altering the device geometry would require altering the device fabrication process and can compromise the device""s performance and reduce its effectiveness.
There is thus a need in the art for method of HBT fabrication that reduces emitter to base capacitance in the HBT. More particularly, there is a need for a method that will limit Ceb without impacting the HBT device geometry and diminishing its performance thereby. Further, there is a need in the art for a method which is practical to implement and which will reduce Ceb effectively.
The present invention is directed to method to reduce emitter to base capacitance (xe2x80x9cCebxe2x80x9d) and related structure. In one embodiment, the invention results in a heterojunction bipolar transistor (xe2x80x9cHBTxe2x80x9d) with an emitter to base capacitance which is lower than that of similar devices fabricated utilizing conventional fabrication methods. Further, the invention achieves the reduction in Ceb without adversely impacting the HBT device geometry or impacting its performance. Moreover, the present invention is practical to implement.
According to one embodiment of the invention, a base region is grown on a transistor region. A dielectric layer is next deposited over the base region. The dielectric layer can comprise, for example, silicon dioxide, silicon nitride, or a suitable low-k dielectric. Subsequently, an opening is fabricated in the dielectric layer, and an emitter layer is formed on top of the dielectric layer and in the opening. Thereafter, an anisotropic and polymerizing etch chemistry is utilized to etch the emitter layer down to a first depth, forming an emitter region in the opening. Next, a non-polymerizing etch chemistry having isotropic components is used to create a notch in the dielectric layer below the emitter region. The formation of the notch reduces the overlap area of a capacitor that forms between the emitter region and the base region, i.e. the emitter to base capacitance. The reduction in the size of the overlap area translates to a reduction in the emitter to base capacitance.
Moreover, a HBT structure can be fabricated in which the extrinsic emitter region and the extrinsic base region are separated by a first notched dielectric segment. The extrinsic emitter region has a polymerized surface adjacent to a non-polymerized surface of the first notched dielectric segment. The result is a HBT structure wherein the emitter to base capacitance is relatively low.